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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\AEC_APP.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\AGC_APP.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\AUDIO_PROCESS.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\FIR_APP.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\advanced_fir_filter\advanced_fir_filter.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\aec\aec.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\agc\agc.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\fpga_examples\fpga_top_usb_audio.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\fpga_examples\fpga_top_usb_camera.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\fpga_examples\fpga_top_usb_disk.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\fpga_examples\fpga_top_usb_keyboard.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\fpga_examples\fpga_top_usb_serial.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\fpga_examples\fpga_top_usb_serial2.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\gowin_rpll\gowin_rpll.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\i2s_receive\clkdiv.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\i2s_receive\i2s_receive.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\mic_pro\gowin_sdpb\gowin_sdpb.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\mic_pro\mic_data_store.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\mic_pro\mic_led.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\mic_pro\mic_serial.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\mic_pro\xcorr.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\pt8211_drive.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\speaker.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\usb_class\usb_audio_top.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\usb_class\usb_camera_top.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\usb_class\usb_disk_top.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\usb_class\usb_keyboard_top.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\usb_class\usb_serial2_top.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\usb_class\usb_serial_top.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\usbfs_core\usbfs_bitlevel.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\usbfs_core\usbfs_core_top.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\usbfs_core\usbfs_debug_monitor.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\usbfs_core\usbfs_debug_uart_tx.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\usbfs_core\usbfs_packet_rx.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\usbfs_core\usbfs_packet_tx.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\usbfs_core\usbfs_transaction.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.9 Beta-5</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sun Nov 12 13:54:18 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>fpga_top_usb_audio</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 194.691MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.557s, Peak memory usage = 194.691MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.345s, Peak memory usage = 194.691MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.741s, Peak memory usage = 194.691MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.453s, Peak memory usage = 194.691MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.112s, Peak memory usage = 194.691MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 194.691MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 194.691MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 194.691MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.203s, Peak memory usage = 194.691MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.094s, Peak memory usage = 194.691MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 7s, Peak memory usage = 194.691MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.521s, Peak memory usage = 194.691MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 201.941MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 13s, Elapsed time = 0h 0m 14s, Peak memory usage = 201.941MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>20</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>19</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>6</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>11</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIOBUF</td>
<td>2</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>8932</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFF</td>
<td>81</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFE</td>
<td>24</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFS</td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFR</td>
<td>15</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>6</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFP</td>
<td>14</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>51</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFC</td>
<td>3551</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>5179</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFNR</td>
<td>8</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>5537</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>2616</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>1683</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>1238</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>2464</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>2464</td>
</tr>
<tr>
<td class="label"><b>SSRAM </b></td>
<td>256</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspRAM16SDP4</td>
<td>256</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>94</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>94</td>
</tr>
<tr>
<td class="label"><b>DSP </b></td>
<td></td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspMULT18X18</td>
<td>32</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspMULT36X36</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspMULTADDALU18X18</td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU54D</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>9</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPX9B</td>
<td>6</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbsppROMX9</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>CLOCK </b></td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbsprPLL</td>
<td>1</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>9631(5631 LUT, 2464 ALU, 256 RAM16) / 20736</td>
<td>47%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>8932 / 16173</td>
<td>56%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>8932 / 16173</td>
<td>56%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>9 / 46</td>
<td>20%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>clk27mhz</td>
<td>Base</td>
<td>37.037</td>
<td>27.0</td>
<td>0.000</td>
<td>18.519</td>
<td> </td>
<td> </td>
<td>clk27mhz_ibuf/I </td>
</tr>
<tr>
<td>dsp_shei_t/agc_ins/your_instance_name/AGC_top_inst/n52_6</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>dsp_shei_t/agc_ins/your_instance_name/AGC_top_inst/n52_s2/O </td>
</tr>
<tr>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_13</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_s1/F </td>
</tr>
<tr>
<td>mic_serial_inst/microphoneIns/clk27mTo3m/n26_6</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>mic_serial_inst/microphoneIns/clk27mTo3m/n26_s2/O </td>
</tr>
<tr>
<td>sk9822_dir/clk_delay[4]_3</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>sk9822_dir/clk_delay_4_s0/Q </td>
</tr>
<tr>
<td>u_usb_audio/HP_BCK_d_2</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>u_usb_audio/clk_1p536m_s1/Q </td>
</tr>
<tr>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>16.667</td>
<td>60.0</td>
<td>0.000</td>
<td>8.333</td>
<td>clk27mhz_ibuf/I</td>
<td>clk27mhz</td>
<td>your_instance_name/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>your_instance_name/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>16.667</td>
<td>60.0</td>
<td>0.000</td>
<td>8.333</td>
<td>clk27mhz_ibuf/I</td>
<td>clk27mhz</td>
<td>your_instance_name/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>your_instance_name/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>33.333</td>
<td>30.0</td>
<td>0.000</td>
<td>16.667</td>
<td>clk27mhz_ibuf/I</td>
<td>clk27mhz</td>
<td>your_instance_name/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>50.000</td>
<td>20.0</td>
<td>0.000</td>
<td>25.000</td>
<td>clk27mhz_ibuf/I</td>
<td>clk27mhz</td>
<td>your_instance_name/rpll_inst/CLKOUTD3 </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clk27mhz</td>
<td>27.0(MHz)</td>
<td>202.0(MHz)</td>
<td>7</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>dsp_shei_t/agc_ins/your_instance_name/AGC_top_inst/n52_6</td>
<td>100.0(MHz)</td>
<td>771.6(MHz)</td>
<td>2</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>mic_serial_inst/microphoneIns/clk3mTows/n43_13</td>
<td>100.0(MHz)</td>
<td>365.5(MHz)</td>
<td>4</td>
<td>TOP</td>
</tr>
<tr>
<td>4</td>
<td>mic_serial_inst/microphoneIns/clk27mTo3m/n26_6</td>
<td>100.0(MHz)</td>
<td>493.8(MHz)</td>
<td>3</td>
<td>TOP</td>
</tr>
<tr>
<td>5</td>
<td>sk9822_dir/clk_delay[4]_3</td>
<td>100.0(MHz)</td>
<td>286.2(MHz)</td>
<td>5</td>
<td>TOP</td>
</tr>
<tr>
<td>6</td>
<td>u_usb_audio/HP_BCK_d_2</td>
<td>100.0(MHz)</td>
<td>370.9(MHz)</td>
<td>4</td>
<td>TOP</td>
</tr>
<tr>
<td>7</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
<td>60.0(MHz)</td>
<td>190.3(MHz)</td>
<td>7</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.911</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>23.021</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.110</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/audio_lo_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>my_spk/u_pt8211_drive_0/idata_r_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_usb_audio/HP_BCK_d_2[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.696</td>
<td>1.029</td>
<td>tCL</td>
<td>RR</td>
<td>8166</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>17.876</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_usb_audio/audio_lo_4_s0/CLK</td>
</tr>
<tr>
<td>18.108</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>u_usb_audio/audio_lo_4_s0/Q</td>
</tr>
<tr>
<td>18.345</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s23/I1</td>
</tr>
<tr>
<td>18.900</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s23/F</td>
</tr>
<tr>
<td>19.137</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s16/I1</td>
</tr>
<tr>
<td>19.692</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s16/F</td>
</tr>
<tr>
<td>19.929</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s10/I0</td>
</tr>
<tr>
<td>20.446</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s10/F</td>
</tr>
<tr>
<td>20.683</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s4/I0</td>
</tr>
<tr>
<td>21.200</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s4/F</td>
</tr>
<tr>
<td>21.437</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s1/I1</td>
</tr>
<tr>
<td>21.992</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>my_spk/u_pt8211_drive_0/n33_s1/F</td>
</tr>
<tr>
<td>22.229</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n47_s0/I1</td>
</tr>
<tr>
<td>22.784</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n47_s0/F</td>
</tr>
<tr>
<td>23.021</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/idata_r_1_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_usb_audio/HP_BCK_d_2</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>27</td>
<td>u_usb_audio/clk_1p536m_s1/Q</td>
</tr>
<tr>
<td>20.180</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/idata_r_1_s0/CLK</td>
</tr>
<tr>
<td>20.145</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>my_spk/u_pt8211_drive_0/idata_r_1_s0</td>
</tr>
<tr>
<td>20.110</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/idata_r_1_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-1.029</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.254, 63.246%; route: 1.659, 32.245%; tC2Q: 0.232, 4.509%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.911</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>23.021</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.110</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/audio_lo_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>my_spk/u_pt8211_drive_0/idata_r_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_usb_audio/HP_BCK_d_2[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.696</td>
<td>1.029</td>
<td>tCL</td>
<td>RR</td>
<td>8166</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>17.876</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_usb_audio/audio_lo_4_s0/CLK</td>
</tr>
<tr>
<td>18.108</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>u_usb_audio/audio_lo_4_s0/Q</td>
</tr>
<tr>
<td>18.345</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s23/I1</td>
</tr>
<tr>
<td>18.900</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s23/F</td>
</tr>
<tr>
<td>19.137</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s16/I1</td>
</tr>
<tr>
<td>19.692</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s16/F</td>
</tr>
<tr>
<td>19.929</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s10/I0</td>
</tr>
<tr>
<td>20.446</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s10/F</td>
</tr>
<tr>
<td>20.683</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s4/I0</td>
</tr>
<tr>
<td>21.200</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s4/F</td>
</tr>
<tr>
<td>21.437</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s1/I1</td>
</tr>
<tr>
<td>21.992</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>my_spk/u_pt8211_drive_0/n33_s1/F</td>
</tr>
<tr>
<td>22.229</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n46_s0/I1</td>
</tr>
<tr>
<td>22.784</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n46_s0/F</td>
</tr>
<tr>
<td>23.021</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/idata_r_2_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_usb_audio/HP_BCK_d_2</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>27</td>
<td>u_usb_audio/clk_1p536m_s1/Q</td>
</tr>
<tr>
<td>20.180</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/idata_r_2_s0/CLK</td>
</tr>
<tr>
<td>20.145</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>my_spk/u_pt8211_drive_0/idata_r_2_s0</td>
</tr>
<tr>
<td>20.110</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/idata_r_2_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-1.029</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.254, 63.246%; route: 1.659, 32.245%; tC2Q: 0.232, 4.509%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.911</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>23.021</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.110</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/audio_lo_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>my_spk/u_pt8211_drive_0/idata_r_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_usb_audio/HP_BCK_d_2[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.696</td>
<td>1.029</td>
<td>tCL</td>
<td>RR</td>
<td>8166</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>17.876</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_usb_audio/audio_lo_4_s0/CLK</td>
</tr>
<tr>
<td>18.108</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>u_usb_audio/audio_lo_4_s0/Q</td>
</tr>
<tr>
<td>18.345</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s23/I1</td>
</tr>
<tr>
<td>18.900</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s23/F</td>
</tr>
<tr>
<td>19.137</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s16/I1</td>
</tr>
<tr>
<td>19.692</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s16/F</td>
</tr>
<tr>
<td>19.929</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s10/I0</td>
</tr>
<tr>
<td>20.446</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s10/F</td>
</tr>
<tr>
<td>20.683</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s4/I0</td>
</tr>
<tr>
<td>21.200</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s4/F</td>
</tr>
<tr>
<td>21.437</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s1/I1</td>
</tr>
<tr>
<td>21.992</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>my_spk/u_pt8211_drive_0/n33_s1/F</td>
</tr>
<tr>
<td>22.229</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n45_s0/I1</td>
</tr>
<tr>
<td>22.784</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n45_s0/F</td>
</tr>
<tr>
<td>23.021</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/idata_r_3_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_usb_audio/HP_BCK_d_2</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>27</td>
<td>u_usb_audio/clk_1p536m_s1/Q</td>
</tr>
<tr>
<td>20.180</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/idata_r_3_s0/CLK</td>
</tr>
<tr>
<td>20.145</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>my_spk/u_pt8211_drive_0/idata_r_3_s0</td>
</tr>
<tr>
<td>20.110</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/idata_r_3_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-1.029</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.254, 63.246%; route: 1.659, 32.245%; tC2Q: 0.232, 4.509%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.911</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>23.021</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.110</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/audio_lo_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>my_spk/u_pt8211_drive_0/idata_r_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_usb_audio/HP_BCK_d_2[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.696</td>
<td>1.029</td>
<td>tCL</td>
<td>RR</td>
<td>8166</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>17.876</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_usb_audio/audio_lo_4_s0/CLK</td>
</tr>
<tr>
<td>18.108</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>u_usb_audio/audio_lo_4_s0/Q</td>
</tr>
<tr>
<td>18.345</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s23/I1</td>
</tr>
<tr>
<td>18.900</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s23/F</td>
</tr>
<tr>
<td>19.137</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s16/I1</td>
</tr>
<tr>
<td>19.692</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s16/F</td>
</tr>
<tr>
<td>19.929</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s10/I0</td>
</tr>
<tr>
<td>20.446</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s10/F</td>
</tr>
<tr>
<td>20.683</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s4/I0</td>
</tr>
<tr>
<td>21.200</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s4/F</td>
</tr>
<tr>
<td>21.437</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s1/I1</td>
</tr>
<tr>
<td>21.992</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>my_spk/u_pt8211_drive_0/n33_s1/F</td>
</tr>
<tr>
<td>22.229</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n44_s0/I1</td>
</tr>
<tr>
<td>22.784</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n44_s0/F</td>
</tr>
<tr>
<td>23.021</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/idata_r_4_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_usb_audio/HP_BCK_d_2</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>27</td>
<td>u_usb_audio/clk_1p536m_s1/Q</td>
</tr>
<tr>
<td>20.180</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/idata_r_4_s0/CLK</td>
</tr>
<tr>
<td>20.145</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>my_spk/u_pt8211_drive_0/idata_r_4_s0</td>
</tr>
<tr>
<td>20.110</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/idata_r_4_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-1.029</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.254, 63.246%; route: 1.659, 32.245%; tC2Q: 0.232, 4.509%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.911</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>23.021</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.110</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/audio_lo_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>my_spk/u_pt8211_drive_0/idata_r_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_usb_audio/HP_BCK_d_2[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>17.696</td>
<td>1.029</td>
<td>tCL</td>
<td>RR</td>
<td>8166</td>
<td>your_instance_name/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>17.876</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_usb_audio/audio_lo_4_s0/CLK</td>
</tr>
<tr>
<td>18.108</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>u_usb_audio/audio_lo_4_s0/Q</td>
</tr>
<tr>
<td>18.345</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s23/I1</td>
</tr>
<tr>
<td>18.900</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s23/F</td>
</tr>
<tr>
<td>19.137</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s16/I1</td>
</tr>
<tr>
<td>19.692</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s16/F</td>
</tr>
<tr>
<td>19.929</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s10/I0</td>
</tr>
<tr>
<td>20.446</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s10/F</td>
</tr>
<tr>
<td>20.683</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s4/I0</td>
</tr>
<tr>
<td>21.200</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s4/F</td>
</tr>
<tr>
<td>21.437</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n33_s1/I1</td>
</tr>
<tr>
<td>21.992</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>my_spk/u_pt8211_drive_0/n33_s1/F</td>
</tr>
<tr>
<td>22.229</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n43_s0/I1</td>
</tr>
<tr>
<td>22.784</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/n43_s0/F</td>
</tr>
<tr>
<td>23.021</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/idata_r_5_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>u_usb_audio/HP_BCK_d_2</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>27</td>
<td>u_usb_audio/clk_1p536m_s1/Q</td>
</tr>
<tr>
<td>20.180</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/idata_r_5_s0/CLK</td>
</tr>
<tr>
<td>20.145</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>my_spk/u_pt8211_drive_0/idata_r_5_s0</td>
</tr>
<tr>
<td>20.110</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>my_spk/u_pt8211_drive_0/idata_r_5_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-1.029</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.254, 63.246%; route: 1.659, 32.245%; tC2Q: 0.232, 4.509%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.180, 100.000%</td></tr>
</table>
<br/>
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